Judul : AMD's stacked 3D V-Cache chiplet tech can triple a processor's L3 cache
link : AMD's stacked 3D V-Cache chiplet tech can triple a processor's L3 cache
AMD's stacked 3D V-Cache chiplet tech can triple a processor's L3 cache
Developed in collaboration with TSMC, AMD’s first application of the 3D chiplet tech is a vertical cache addition for its high-end processors. In a nutshell, AMD used a process called through-silicon vias (TSVs) to stack additional L3 cache on top of the compute chiplets.
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